MC68HC05X4 Datasheet, PDF (106/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Core Timer
Freescale Semiconductor, Inc.
If the COP circuit times out, an internal reset is generated and the normal
reset vector is fetched. COP timeout is prevented by writing a ‘0’ to bit 0
of address $1FF0. When the COP is cleared, only the final
divide-by-eight stage is cleared (see Figure 1).
The COP function is a mask option, enabled or disabled during device
manufacture.
Core timer registers
Core timer control
and status register
(CTCSR)
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
CTOF RTIF CTOE RTIE
0
0
RT1
RT0
Reset: u
u
0
0
0
0
1
1
Figure 2. Core Timer Control/Status Register (CTCSR)
CTOF — Core timer overflow
1 = This read-only flag is set whenever a core timer overflow
occurs.
0 = No core timer overflow has occurred.
This bit is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOE is set. When
set, the bit may be cleared by writing a ‘0’ to it.
RTIF — Real time interrupt flag
1 = This read-only flag is set when the pre-selected RTI period has
elapsed. The RTI period is selected using the RT0 and RT1
bits as shown in Table 1.
0 = The pre-selected RTI period has not elapsed.
MC68HC05X4 Rev 1.0
Core Timer
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Go to: www.freescale.com
4-ctimer