MC68HC05X4 Datasheet, PDF (113/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

5-ptimer
Freescale Semiconductor, Inc.
16-Bit Programmable Timer
Counter registers
Address: $001A
Bit 15
14
13
12
11
10
9
Bit 8
Reset: 1
1
1
1
1
1
1
1
Figure 4. Alternate Counter High Register (ACH)
Address: $001B
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 1
1
1
1
1
1
0
0
Figure 5. Alternate Counter High Register (ACL)
The double-byte, free-running counter can be read from either of two
locations, $18 – $19 (counter register) or $1A – $1B (alternate counter
register). A read from only the less significant byte (LSB) of the
free-running counter ($19 or $1B) receives the count value at the time of
the read. If a read of the free-running counter or alternate counter
register first addresses the more significant byte (MSB) ($18 or $1A), the
LSB is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or alternate counter
register LSB and thus completes a read sequence of the total counter
value. In reading either the free-running counter or alternate counter
register, if the MSB is read, the LSB must also be read to complete the
sequence. If the timer overflow flag (TOF) is set when the counter
register LSB is read, then a read of the TSR will clear the flag.
The alternate counter register differs from the counter register only in
that a read of the LSB does not clear TOF. Therefore, to avoid the
possibility of missing timer overflow interrupts due to clearing of TOF, the
alternate counter register should be used where this is a critical issue.
The free-running counter is set to $FFFC during reset and is always a
read-only register. During a power-on reset, the counter is also preset to
$FFFC and begins running after the oscillator start-up delay. Because
the free-running counter is 16 bits preceded by a fixed divide-by-four
16-Bit Programmable Timer
For More Information On This Product,
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MC68HC05X4 Rev 1.0