MC68HC05X4 Datasheet, PDF (77/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Motorola CAN
Interface to the MC68HC05X4 CPU
MCAN control
register (CCNTRL)
This register may be read or written to by the MCU; only the RR bit is
affected by the MCAN.
Address: $0020
Bit 7
6
5
4
3
2
1
Bit 0
MODE SPD
OIE
EIE
TIE
RIE
RR
External Reset: 0
u
-
u
u
u
u
1
Reset: with RR bit set 0
u
-
u
u
u
u
1
Figure 4. MCAN Control Register (CCNTRL)
NOTE: Only the RR bit in this register can be written when the RR bit is set.
MODE — Undefined mode
This bit must never be set by the CPU as this would result in the
transmit and receive buffers being mapped out of memory. The bit is
cleared on reset, and should be left in this state for normal operation.
SPD — Speed mode
1 = Slow – Bus line transitions from both ‘recessive’ to ‘dominant’ and
from ‘dominant’ to ‘recessive’ will be used for resynchronization.
0 = Fast – Only transitions from ‘recessive’ to ‘dominant’ will be
used for resynchronization.
OIE — Overrun interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever the
Overrun Status bit gets set.
0 = Disabled – The CPU will get no overrun interrupt request.
EIE — Error interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever the
error status or bus status bits in the CSTAT register change.
0 = Disabled – The CPU will get no error interrupt request.
TIE — Transmit interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever a
message has been successfully transmitted, or when the transmit
buffer is accessible again following an ABORT command.
0 = Disabled – The CPU will get no transmit interrupt request.
9-mcan
Motorola CAN
For More Information On This Product,
Go to: www.freescale.com
MC68HC05X4 Rev 1.0