MC68HC05X4 Datasheet, PDF (82/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Motorola CAN
Freescale Semiconductor, Inc.
MCAN status
register (CSTAT)
This is a read only register; only the MCAN can change its contents.
Address: $0022
Bit 7
6
5
4
3
2
1
Bit 0
BS
ES
TS
RS
TCS
TBA
DO
RBS
External Reset: 0
0
0
0
1
1
0
0
Reset: with RR bit set u
u
0
0
1
1
0
0
Figure 6. MCAN Status Register (CSTAT)
BS — Bus status
This bit is set (off-bus) by the MCAN when the transmit error counter
reaches 256. The MCAN will then set RR and will remain off-bus until
the CPU clears RR again. At this point the MCAN will wait for 128
successive occurrences of a sequence of 11 recessive bits before
clearing BS and resetting the read and write error counters. While
off-bus the MCAN does not take part in bus activities.
1 = Off-bus – The MCAN is not participating in bus activities.
0 = On-bus – The MCAN is operating normally.
ES — Error status
1 = Error – Either the read or the write error counter has reached
the CPU warning limit of 96.
0 = Neither of the error counters has reached 96.
TS — Transmit status
1 = Transmit – The MCAN has started to transmit a message.
0 = Idle – If the receive status bit is also clear then the MCAN is
idle; otherwise it is in receive mode.
RS — Receive status
1 = Receive – The MCAN entered receive mode from idle, or by
losing arbitration during transmission.
0 = Idle – If the transmit status bit is also clear then the MCAN is
idle; otherwise it is in transmit mode.
NOTE: RS will not be set during a bus failure with a permanent dominant bus
level.
MC68HC05X4
Motorola CAN
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Go to: www.freescale.com
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