MC68HC05X4 Datasheet, PDF (66/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel input/output ports
Port registers
The following sections explain in detail the individual bits in the data and
control registers associated with the ports.
Port A data
register (PADR)
Each bit can be configured as input or output via the corresponding data
direction bit in the port A DDR.
Reset does not affect the state of this register.
NOTE:
If the AWPS bit in the PCR is set then this location becomes the port A
wired-OR interrupt enable register. Writing a ‘1’ to any bit enables WOI
on the corresponding port A line.
Port B data register
(PBDR)
Each bit can be configured as input or output via the corresponding data
direction bit in the port B DDR.
Reset does not affect the state of this register.
Port configuration
register (PCR)
Address: $0005
Bit 7
6
5
4
3
2
1
WOIF TIMEN CAF BPDE0 BWE
Reset: -
-
0
0
0
0
0
Figure 2. Port Configuration Register (PCR)
Bit 0
AWPS
0
WOIF — Wired-OR interrupt flag
1 = Indicates that a wired-OR interrupt has been received. A CPU
interrupt request is generated if WOIE is set on port A or port B.
0 = The flag is cleared by writing a ‘0’ to it.
TIMEN — Timer enable
CAF — Indicates when MCAN is asleep
MC68HC05X4 Rev 1.0
Parallel input/output ports
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4-ports