MC68HC05X4 Datasheet, PDF (63/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel input/output ports
General Description
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Port registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port A data register (PADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port B data register (PBDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port configuration register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port A data direction register (PADDR) . . . . . . . . . . . . . . . . . . . . . 67
Port B data direction register (PBDDR) . . . . . . . . . . . . . . . . . . . . . 67
Introduction
In single chip mode there are 16 lines arranged as two 8-bit I/O ports.
The I/O ports are programmable as either inputs or outputs under
software control of the data direction registers. Wired-OR Interrupt
capability (refer to Resets) and/or a pull-down device can be activated
under software control on each I/O pin.
To avoid glitches on the output pins data should be written to the I/O port
data register before setting the pin to output mode, by writing a ‘1’ to the
corresponding data direction register.
1-ports
Parallel input/output ports
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MC68HC05X4 Rev 1.0