MC68HC05X4 Datasheet, PDF (50/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets, Interrupts and Low Power Modes
RTI instruction (return from interrupt) causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on. When the current instruction is complete, the
processor checks all pending hardware interrupts. If interrupts are not
masked (CCR I-bit clear) and the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing; otherwise, the
next instruction is fetched and executed.
If both an external interrupt and a timer interrupt are pending after an
instruction execution, the external interrupt is serviced first.
Table 1 shows the relative priority of all the possible interrupt sources.
Figure 2 shows the interrupt processing flow.
Table 1. Interrupt priorities
Source
Reset
Software interrupt (SWI)
CAN interrupt (CIRQ)
Core timer (CTIMER)
Wired-OR interrupt
Programmable timer
Register
—
—
CINT
CTCSR
PCR
TSR
Flags
—
—
WIF, OIF, EIF, TIF, RIF
CTOF, RTIF
WOIF
ICF, OFC, TOF
Vector address
$1FFE, $1FFF
$1FFC, $1FFD
$1FFA, $1FFB
$1FF8, $1FF9
$1FF6, $1FF7
$1FF4, $1FF5
Priority
highest
lowest
Non-maskable
software interrupt
(SWI)
The software interrupt (SWI) is an executable instruction and a
non-maskable interrupt: it is executed regardless of the state of the I-bit
in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after
interrupts that were pending when the SWI was fetched, but before
interrupts generated after the SWI was fetched. The SWI interrupt
service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
MC68HC05X4
Resets, Interrupts and Low Power Modes
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4-resets