MC68HC05X4 Datasheet, PDF (107/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Core Timer
Core timer registers
This bit is set when the output of the chosen stage becomes active;
an interrupt request will be generated if RTIE is set. When set, the bit
may be cleared by writing a ‘0’ to it.
CTOE — Core timer overflow interrupt enable
1 = A core timer overflow interrupt will be generated if CTOF is set
and the I-bit in the CCR is clear.
0 = No core timer overflow interrupt will be generated regardless of
the state of the CTOF flag and the I-bit.
RTIE — Real time interrupt enable
0 = A real time interrupt will be generated if RTIF is set and the I-bit
in the CCR is clear.
0 = No real time interrupt will be generated regardless of the state
of the RTIF flag and the I-bit.
RT1, RT0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt
circuitry. Reset sets both RT0 and RT1 to one, selecting the lowest
periodic rate and therefore the maximum time in which to alter them if
necessary. The COP reset times are also determined by these two
bits. Care should be taken when altering RT0 and RT1 if a timeout is
imminent, or if the timeout period is uncertain. If the selected tap is
modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing the RTI taps.
See Table 1 for some example RTI periods.
Table 1. Example RTI periods
RT1
RT0
Division
ratio
00
2¹⁴
01
2¹⁵
10
2¹⁶
11
2¹⁷
Bus frequency
f_OP = 500 kHz
RTI
period
Minimum
COP
period
31.3ms 218.8ms
62.5ms 437.5ms
125ms 875.0ms
250ms 1.75s
Bus frequency
f_OP = 1 MHz
RTI
period
Minimum
COP
period
15.6ms 109.4ms
31.3ms 218.8ms
62.5ms 437.5ms
125.1ms 875.0ms
Bus frequency
f_OP = 2 MHz
RTI
period
Minimum
COP
period
7.8ms 54.7ms
15.6ms 109.4ms
31.3ms 218.8ms
62.5ms 437.5ms
5-ctimer
Core Timer
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MC68HC05X4 Rev 1.0