MC68HC05X4 Datasheet, PDF (78/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Motorola CAN
Freescale Semiconductor, Inc.
NOTE:
When setting TIE while TCS or TBA is set, no interrupt will be requested.
Successful transmission must occur after setting the TIE bit to get an
interrupt flag.
RIE — Receive interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever a
message has been received free of errors.
0 = Disabled – The CPU will get no receive interrupt request.
RR — Reset request
When the MCAN detects that RR has been set it aborts the current
transmission or reception of a message and enters the reset state. A
reset request may be generated by either an external reset or by the
CPU or by the MCAN. The RR bit can be cleared only by the CPU.
After the RR bit has been cleared, the MCAN will start normal
operation in one of two ways. If RR was generated by an external
reset or by the CPU, then the MCAN starts normal operation after the
first occurrence of 11 recessive bits. The MCAN module is not
synchronized to the bus until the 11 recessive bits have been
received. When the SLEEP bit is set during this non synchronous
state, an immediate wake-up wil be generated by the MCAN module.
If, however, the RR was generated by the MCAN due to the BS bit
being set (see MCAN status register (CSTAT)) the MCAN waits for
128 occurrences of 11 recessive bits before starting normal
operation.
A reset request should not be generated by the CPU during a
message transmission. Ensure that a message is not being
transmitted as follows:
if TCS in CSTAT is clear – set AT in CCOM (use STA or STX),
read CSTAT.
if TS in CSTAT is set – wait until TS is clear.
Note that a CPU-generated reset request does not change the values
in the transmit and receive error counters.
1 = Present – MCAN will be reset.
0 = Absent – MCAN will operate normally.
NOTE: The following registers may only be accessed when reset request =
present: CACC, CACM, CBT0, CBT1, and COCNTRL.
MC68HC05X4
Motorola CAN
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