MC68HC05X4 Datasheet, PDF (54/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets, Interrupts and Low Power Modes
During the WAIT mode, the I-bit in the CCR is cleared to enable
interrupts. All other registers, memory, and input/output lines remain in
their previous state. The Core Timer may be enabled to allow a periodic
exit from the WAIT mode. See Core timer during WAIT.
Data retention
mode
The contents of the RAM are retained at supply voltages as low as
2.0 Vdc. This is called the data retention mode, in which data is
maintained but the device is not guaranteed to operate.
For lowest power consumption in data retention mode the device should
be put into STOP mode before reducing the supply voltage, to ensure
that all the clocks are stopped. If the device is not in STOP mode then it
is recommended that RESET be held low whilst the power supply is
outwith the normal operating range, to ensure that processing is
suspended in an orderly manner.
– Recovery from data retention mode, after the power supply
has been restored, is by an external interrupt, or by pulling the
RESET line high
MC68HC05X4
Resets, Interrupts and Low Power Modes
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8-resets