MC68HC05RC17 Datasheet, PDF (91/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Phase-Locked Loop (PLL) Synthesizer
Operation During Stop Mode
NOTE:
For the MC68HC05RC17, the 4.194-MHz bus clock frequency should
not be selected. The 2.097-MHz bus clock frequency should not be
selected when running the part below V_DD = 3.0 V.
10.4 Operation During Stop Mode
The PLL is switched to low-frequency bus rate and is turned off
temporarily when STOP is executed. Coming out of stop mode with an
external IRQ, the PLL is turned on with the same configuration it had
before going into STOP with the exception of BCS which is reset.
Otherwise, the PLL control register is in the reset condition.
10.5 Noise Immunity
The MCU should be insulated as much as possible from noise in the
system. These steps are recommend to help prevent problems due to
noise injection.
1. The application environment should be designed so that the MCU
is not near signal traces which switch often, such as a clock signal.
2. The oscillator circuit for the MCU should be placed as close as
possible to the OSC1 and OSC2 pins on the MCU.
3. To minimize noise, all power pins should be filtered by using
bypass capacitors placed as close as possible to the MCU.
See the application note Designing for Electromagnetic Compatibility
(EMC) with HCMOS Microcontrollers, available through the Freescale
Literature Distribution Center, document number AN1050/D.
MC68HC05RC17 — Rev. 2.0
General Release Specification
Phase-Locked Loop (PLL) Synthesizer
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