MC68HC05RC17 Datasheet, PDF (65/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Core Timer
Core Timer Control and Status Register
8.3 Core Timer Control and Status Register
The CTCSR contains the timer interrupt flag, the timer interrupt enable
bits, and the real-time interrupt rate select bits. Figure 8-2 shows the
value of each bit in the CTCSR when coming out of reset.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read: CTOF RTIF
0
0
TOFE RTIE
RT1
RT0
Write:
TOFC RTFC
Reset: 0
0
0
0
0
0
1
1
= Unimplemented
Figure 8-2. Core Timer Control and Status Register (CTCSR)
CTOF — Core Timer Overflow
CTOF is a read-only status bit set when the 8-bit ripple counter rolls
over from $FF to $00. Clearing the CTOF is done by writing a 1 to
TOFC. Writing to this bit has no effect. Reset clears CTOF.
RTIF — Real-Time Interrupt Flag
The real-time interrupt circuit consists of a 3-stage divider and a one-
of-four selector. The clock frequency that drives the RTI circuit is E/2¹²
(or E ÷ 4096) with three additional divider stages, giving a maximum
interrupt period of 16 milliseconds at a bus rate of 2.024 MHz. RTIF is
a clearable, read-only status bit and is set when the output of the
chosen (one-of-four selection) stage goes active. Clearing the RTIF is
done by writing a 1 to RTFC. Writing has no effect on this bit. Reset
clears RTIF.
TOFE — Timer Overflow Enable
When this bit is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears this bit.
RTIE — Real-Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
MC68HC05RC17 — Rev. 2.0
General Release Specification
Core Timer
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