MC68HC05RC17 Datasheet, PDF (43/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Interrupts
Hardware Interrupts
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The three
types of hardware interrupts are explained in the following sections.
4.7 External Interrupt (IRQ/Port B Keyscan)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-2.
NOTE:
The BIH and BIL instructions will apply to the level on the IRQ pin itself
and to the output of the logic OR function with the port B IRQ interrupts.
The states of the individual port B pins can be checked by reading the
appropriate port B pins as inputs.
The IRQ pin is one source of an external interrupt. All port B pins (PB0
through PB7) act as other external interrupt sources if the
pullup/interrupt feature is enabled as speci ed b y the user.
EIMSK
IRQ PIN
PORT B INTERRUPT/KEYSCAN
IRQ VECTOR FETCH
RST
LEVEL
(MASK OPTION)
V_DD
IRQ
LATCH
R
Figure 4-2. IRQ Function Block Diagram
TO BIH & BIL
INSTRUCTION
SENSING
TO IRQ
PROCESSING
IN CPU
MC68HC05RC17 — Rev. 2.0
General Release Specification
Interrupts
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