MC68HC05RC17 Datasheet, PDF (53/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Resets
Internal Resets
5.5.2.5 COP Register
The COP register is shared with the LSB of an unimplemented user
interrupt vector as shown in Figure 5-3. Reading this location returns
whatever user data has been programmed at this location. Writing a 0 to
the COPR bit in this location clears the COP watchdog timer.
Address: $3FF0
Bit 7
6
5
4
3
2
1
Read: X
X
X
X
X
X
X
Write:
Reset: —
—
—
—
—
—
—
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
Bit 0
X
COPR
0
5.5.3 Illegal Address
An illegal address reset is generated when the CPU attempts to fetch an
instruction from I/O address space ($0000 to $001F).
MC68HC05RC17 — Rev. 2.0
General Release Specification
Resets
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