MC68HC05RC17 Datasheet, PDF (34/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
3.3 CPU Registers
The MCU contains five registers as shown in Figure 3-1. The interrupt
stacking order is shown in Figure 3-2.
7
7
13
PC
13
7
0 0 0 0 0 0 11
0
A
0
X
0
0
SP
CCR
H INZC
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER
STACK POINTER
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
0 _STACK
INCREASING
MEMORY
ADDRESSES
1 1 1 CONDITION CODE REGISTER _I
R
E
T
U
R
N
ACCUMULATOR
INDEX REGISTER
PCH
N
T
E
R
R
U
P
PCL
T
DECREASING
MEMORY
ADDRESSES
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
General Release Specification
MC68HC05RC17 — Rev. 2.0
Central Processor Unit (CPU)
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