MC68HC05RC17 Datasheet, PDF (66/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Core Timer
Freescale Semiconductor, Inc.
TOFC — Timer Overflow Flag Clear
When a 1 is written to this bit, CTOF is cleared. Writing a 0 has no
effect on the CTOF bit. This bit always reads as 0.
RTFC — Real-Time Interrupt Flag Clear
When a 1 is written to this bit, RTIF is cleared. Writing a 0 has no effect
on the RTIF bit. This bit always reads as 0.
RT1 and RT0 — Real-Time Interrupt Rate Select
These two bits select one of four taps from the real-time interrupt
circuit. Refer to Table 8-1. Reset sets these two bits which selects the
lowest periodic rate and gives the maximum time in which to alter
these bits if necessary. Care should be taken when altering RT0 and
RT1 if the time out period is imminent or uncertain. If the selected tap
is modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing RTI taps.
Table 8-1. RTI and COP Rates at 4.096-MHz Oscillator
RTI Rate
2.048-MHz Bus
2 ms
2¹² ÷ E
4 ms
2¹³ ÷ E
8 ms
2¹⁴ ÷ E
16 ms
2¹⁵ ÷ E
RT1 and RT0
00
01
10
11
Minimum COP Rates
2.048-MHz Bus
(2¹⁵–2¹²)/E
14 ms
(2¹⁶–2¹³)/E
28 ms
(2¹⁷–2¹⁴)/E
56 ms
(2¹⁸–2¹⁵)/E
112 ms
General Release Specification
MC68HC05RC17 — Rev. 2.0
Core Timer
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