MC68HC05RC17 Datasheet, PDF (40/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Interrupts
Freescale Semiconductor, Inc.
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
complete.
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, the processor will proceed with
interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, stacks the current CPU register state, sets the I bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If
more than one interrupt is pending following the stacking operation, the
interrupt with the highest vector location shown in Table 4-1 will be
serviced first. The SWI is executed the same as any other instruction,
regardless of the I-bit state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $3FF6 through $3FFF as defined in Table 4-1.
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag
Name
Interrupt
CPU
Interrupt
Vector
Address
N/A
N/A Reset
RESET $3FFE–$3FFF
N/A
N/A Software Interrupt
SWI $3FFC–$3FFD
N/A
N/A External Interrupts*
IRQ
$3FFA–$3FFB
MCSR EOC End-of-Cycle Interrupt
CMT
$3FF8–$3FF9
CTCSR
CTOF, Real-Time Interrupt
RTIF
Core Timer Over o w
CORE
TIMER
$3FF6–$3FF7
*External interrupts include IRQ and port B keyscan sources.
General Release Specification
MC68HC05RC17 — Rev. 2.0
Interrupts
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