MC68HC05RC17 Datasheet, PDF (87/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification — MC68HC05RC17
Section 10. Phase-Locked Loop (PLL) Synthesizer
10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.3 Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .89
10.4 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.5 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.2 Introduction
The phase-locked loop (PLL) consists of a variable bandwidth loop filter,
a voltage controlled oscillator (VCO), a feedback frequency divider, and
a digital phase detector. The PLL requires an external loop filter
capacitor (typically 0.1 µF) connected between XFC and V_DDSYN. This
capacitor should be located as close to the chip as possible to minimize
noise. V_DDSYN is the supply source for the PLL and should be bypassed
to minimize noise. The V_DDSYN bypass cap should be as close as
possible to the chip. V_DDSYN should be at the same potential as V_DD.
The phase detector compares the frequency and phase of the feedback
frequency (t_FB) and the crystal oscillator reference frequency (t_REF) and
generates the output, PCOMP, as shown in Figure 10-1. The output
waveform is then integrated and amplified. The resultant dc voltage is
applied to the voltage controlled oscillator. The output of the VCO is
divided by a variable frequency divider of 128, 64, 32, or 16 to provide
the feedback frequency for the phase detector.
MC68HC05RC17 — Rev. 2.0
General Release Specification
Phase-Locked Loop (PLL) Synthesizer
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