MC68HC05RC17 Datasheet, PDF (88/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Phase-Locked Loop (PLL) Synthesizer
VDDSYN
0.1 µF
OSC1 t_REF
CRYSTAL
OSCILLATOR
PHASE
DETECT
PCOMP
0.1 µF
XFC
LOOP FILTER
t_FB
FREQUENCY
DIVIDER
VCO
PLLOUT
CLOCK
SELECT
BCS
TO CLOCK
GENERATION
CIRCUITRY
PS1 PS0
Figure 10-1. PLL Circuit
To change PLL frequencies, follow this 6-step procedure:
NOTE:
1. Clear BCS to enable the low frequency bus rate
2. Clear PLLON to disable the PLL and select manual high
bandwidth
3. Select the speed using PS1 and PS0
4. Set PLLON to enable the PLL
5. Wait a time of 90% t_PLLS for the PLL frequency to stabilize and
select manual low bandwidth, wait another 10% t_PLLS
Typically, t_PLLS equals 10 ms.
6. Set BCS to switch to the high-frequency bus rate
The user cannot switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of high
frequency operation during the re-configuration of the PLL.
Whenever the PLL is first enabled, the wide bandwidth mode is used.
This enables the PLL frequency to ramp up quickly. When the output
frequency is near the desired frequency, the filter is switched to the
narrow bandwidth mode to make the final frequency more stable.
General Release Specification
MC68HC05RC17 — Rev. 2.0
Phase-Locked Loop (PLL) Synthesizer
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