MC68HC05RC17 Datasheet, PDF (82/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Carrier Modulator Transmitter (CMT)
9.5.3.2 Modulator Control and Status Register
The modulator control and status register (MCSR) contains the
modulator and carrier generator enable (MCGEN), interrupt enable (IE),
mode select (MODE), baseband enable (BASE), extended space
(EXSPC), and external interrupt mask (EIMSK) control bits, divide-by-
two prescaler (DIV2) bit, and the end of cycle (EOC) status bit.
Address: $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read: EOC
Write:
DIV2 EIMSK EXSPC BASE MODE
IE MCGEN
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-7. Modulator Control and Status Register (MCSR)
EOC — End-Of-Cycle Status Flag
1 = End of modulator cycle (counter = SBUFF) has occurred
0 = Current modulation cycle in progress
EOC is set when a match occurs between the contents of the space
period register, SREG, and the down counter. This is recognized as
the end of the modulation cycle. At this time, the counter is initialized
with the (possibly new) contents of the mark period buffer, MBUFF,
and the space period register, SREG, is loaded with the (possibly new)
contents of the space period buffer, SBUFF. This flag is cleared by a
read of the MCSR followed by an access of MDR2 or MDR3. The EOC
flag is cleared by reset.
DIV2 — Divide-by-two prescaler
1 = Divide-by-two prescaler enabled
0 = Divide-by-two prescaler disabled
The divide-by-two prescaler causes the CMT to be clocked at the bus
rate when enabled; 2 x the bus rate when disabled (f_osc). This bit is not
double buffered and so should not be set during a transmission.
General Release Specification
MC68HC05RC17 — Rev. 2.0
Carrier Modulator Transmitter (CMT)
For More Information On This Product,
Go to: www.freescale.com