MC68HC05RC17 Datasheet, PDF (73/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Carrier Modulator Transmitter (CMT)
Carrier Generator
9.4.1 Time Counter
The high/low time counter is a 6-bit up counter. After each increment, the
contents of the counter are compared with the appropriate high or low
count value register. When this value is reached, the counter is reset and
the compare is redirected to the other count value register. Assuming
that the high time count compare register is currently active, a valid
compare will cause the carrier output to be driven low. The counter will
continue to increment and when reaching the value stored in the
selected low count value register, it will be cleared and will cause the
carrier output to be driven high. The cycle repeats, automatically
generating a periodic signal which is directed to the modulator. The
lowest frequency (maximum period) and highest frequency (minimum
period) which can be generated are.
f_min = f_osc ÷ (2 x (2⁶ – 1)) Hz
f_max = f_osc ÷ (2 x 1) Hz
In the general case, the carrier generator output frequency is:
Where:
f_out = f_osc ÷ (Highcount + Lowcount) Hz
0 < Highcount < 64 and
0 < Lowcount < 64
NOTE:
These equations assume the DIV2 bit (bit 6) of the MCSR is clear. When
the DIV2 bit is set, the carrier generator frequency will be half of what is
shown in these equations.
The duty cycle of the carrier signal is controlled by varying the ratio of
high time to low + high time. As the input clock period is fixed, the duty
cycle resolution will be proportional to the number of counts required to
generate the desired carrier period.
Duty Cycle = _{H-----i--g---h----c---o-H---u-i--g-n---ht---c-+---o--L-u--o--n--w--t---c---o----u---n----t}
MC68HC05RC17 — Rev. 2.0
General Release Specification
Carrier Modulator Transmitter (CMT)
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