MC68HC05RC17 Datasheet, PDF (68/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Core Timer
Freescale Semiconductor, Inc.
If the COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU.
The COP remains enabled after execution of the WAIT instruction and
all associated operations apply. If the STOP instruction is disabled,
execution of STOP instruction causes the CPU to execute a no
operation (NOP) instruction. In addition, the COP is prohibited from
being held in reset. This prevents a device lock-up condition.
This COP’s objective is to make it impossible for this device to become
stuck or locked-up and to be sure the COP is able to rescue the part from
any situation where it might entrap itself in abnormal or unintended
behavior. This function is a mask option.
8.6 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
wait mode. The COP is always enabled while in user mode.
General Release Specification
MC68HC05RC17 — Rev. 2.0
Core Timer
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