MC68HC05RC17 Datasheet, PDF (22/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Description
1.5.2 IRQ (Maskable Interrupt Request)
This pin has a mask option as specified by the user that provides one of
two different choices of interrupt triggering sensitivity. The options are:
1. Negative edge-sensitive triggering only
2. Both negative edge-sensitive and level-sensitive triggering
The MCU completes the current instruction before it responds to the
interrupt request. When IRQ goes low for at least one t_ILIH, a logic 1 is
latched internally to signify that an interrupt has been requested. When
the MCU completes its current instruction, the interrupt latch is tested. If
the interrupt latch contains a logic 1 and the interrupt mask bit (I bit) in
the condition code register is clear, the MCU then begins the interrupt
sequence.
If the option is selected to include level-sensitive triggering, the IRQ input
requires an external resistor to V_DD for wired-OR operation.
The IRQ pin contains an internal Schmitt trigger as part of its input to
improve noise immunity.
Refer to Section 4. Interrupts for more detail.
1.5.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal, a ceramic resonator, or an external signal connects to these pins
to provide a system clock. The oscillator frequency is two times the
internal bus rate.
Figure 1-4 shows the recommended circuit when using a crystal. The
crystal and components should be mounted as close as possible to the
input pins to minimize output distortion and startup stabilization time.
A ceramic resonator may be used in place of the crystal in cost-sensitive
applications. Figure 1-4 (a) shows the recommended circuit for using a
ceramic resonator. The manufacturer of the particular ceramic resonator
being considered should be consulted for specific information.
General Release Specification
MC68HC05RC17 — Rev. 2.0
General Description
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