MC68HC05RC17 Datasheet, PDF (76/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Carrier Modulator Transmitter (CMT)
NOTE:
Writing to CHR1 to update IROLN or to CLR1 to update IROLP will also
update the primary carrier high and low data values. Care should be
taken that bits 5–0 of the data to be written to CHR1 or CHL1 should
contain the desired values for the primary carrier high or low data.
9.5 Modulator
The modulator consists of a 12-bit down counter with underflow
detection which is loaded from the modulation mark period from the
mark buffer register, MBUFF. When this counter underflows, the
modulator gate is closed and a 12-bit comparator is enabled which
continually compares the logical complement of the contents of the (still)
decrementing counter with the contents of the modulation space period
register, SREG. When a match is obtained, the modulator control gate
is opened again. Should SREG = 0, the match will be immediate and no
space period will be generated (for instance, for FSK protocols which
require successive bursts of different frequencies). When the match
occurs, the counter is reloaded with the contents of MBUFF, SREG is
reloaded with the contents of its buffer, SBUFF, and the cycle repeats.
The MCGEN bit in the MCSR must be set to enable the modulator timer.
The 12-bit MBUFF and SBUFF registers are accessed through three 8-
bit modulator period registers, MDR1, MDR2, and MDR3.
The modulator can operate in two modes, time or FSK. In time mode the
modulator counts clocks derived from the system oscillator and
modulates a single-carrier frequency or no carrier (baseband). In FSK
mode, the modulator counts carrier periods and instructs the carrier
generator to alternate between two carrier frequencies whenever a
modulation period (mark + space counts) expires.
General Release Specification
MC68HC05RC17 — Rev. 2.0
Carrier Modulator Transmitter (CMT)
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