MC68HC05RC17 Datasheet, PDF (116/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Electrical Specifications
12.8 DC Electrical Characteristics (2.2 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
I_Load = 10.0 µA
I_Load = –10.0 µA
V_OL
—
—
V_OH
V_DD –0.1
—
0.1
V
—
Output High Voltage
(I_Load –0.6 mA) Port A, Port B, Port C (1–7)
(I_Load –2.5 mA) IRO
(I_Load –1.2 mA) Port C (Bit 0)
V_OH
V_DD –0.3 V_DD –0.1
V_DD –0.7 V_DD –0.1
—
—
V
V_DD –0.3 V_DD –0.1
—
Output Low Voltage
(I_Load = 1.0 mA) Port A, Port B, Port C (1–7)
(I_Load = 8.0 mA) IRO
(I_Load = 7.0 mA) Port C (Bit 0)
V_OL
—
—
0.1
0.1
0.3
0.8
V
—
0.1
0.3
Input High Voltage
Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1
V_IH
0.7 x V_DD
—
V_DD
V
Input Low Voltage
Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1
V_IL
V_SS
—
0.4 x V_DD V
Supply Current (see Notes)
Run (f_OP = 1.0 MHz)
Wait with PLL Enabled (f_OP = 1.0 MHz)
Wait with PLL Disabled (f_OP = 16.384 kHz)
Stop
25 ^oC
0 ^oC to +70 ^oC
—
0.5
1.0
mA
—
0.2
0.8
mA
I_DD
—
21.0
40.0
µA
—
0.1
1.0
µA
—
0.1
4.0
µA
I/O Ports Hi-Z Leakage Current
Port A, Port B, Port C
I_OZ
–4
—
4
µA
Input Current
RESET, LPRST, IRQ, OSC1
PB0–PB7 with Pullups Enabled (V_IN = 0.4 x V_DD)
I_In
–0.4
–25
—
–79
0.4
–105
µA
PB0–PB7 with Pullups Enabled (V_IN = 0.7 x V_DD)
–15
–35
–65
Capacitance
Ports (as Input or Output)
RESET, LPRST, IRQ
C_Out
—
—
12
pF
C_INT
—
—
8
NOTES:
1. V_DD = 2.2 Vdc ± 10%, V_SS = 0 Vdc, T_A = 0 °C to +70 °C, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 ^oC only
4. All current measurements represent the summation of current through V_DD and V_DDSYN supply pins.
5. To minimize current consumption in wait mode, disable the PLL before executing the WAIT instruction. Internal bus
speed will be f_osc of crystal ÷ 2.
6. Wait I_DD: only core timer active
7. Run (with PLL enabled) I_DD, wait I_DD (with PLL enabled): Measured using external square wave clock source
(f_OSC = 2.0 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C_L = 20 pF on OSC2. Wait
I_DD (with PLL disabled): Measured using external square wave clock source (f_osc = 33 kHz).
8. Wait, stop I_DD: Port A and port C configured as inputs, port B configured as outputs, V_IL = 0.2 V, V_IH = V_DD –0.2 V
9. Stop I_DD is measured with OSC1 = V_SS.
10. Wait I_DD is affected linearly by the OSC2 capacitance.
11. Pullups are designed to be capable of pulling to V_IH within 25 µs for a 100 pF, 4-kΩ load.
General Release Specification
MC68HC05RC17 — Rev. 2.0
Electrical Specifications
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