MC68HC05RC17 Datasheet, PDF (77/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Carrier Modulator Transmitter (CMT)
Modulator
12 BITS
0
MBUFF
13-BIT DOWN COUNTER *
12
=?
12
SREG *
SBUFF
12 BITS
* DENOTES HIDDEN REGISTER
CLOCK CONTROL
÷8
f_OSC
. CARRIER OUT
LOAD M_.BUFF/SBUFF
MODULATOR GATE
MODULATOR
OUT
SYSTEM CONTROL
PRIMARY/SECONDARY SELECT
MODULATOR
CONTROL/STATUS REGISTER
MODULATOR/
CARRIER GENERATOR
ENABLE
EOC FLAG
EOC INTERRUPT ENABLE
MODE
BASE
DIV2
Figure 9-4. Modulator Block Diagram
9.5.1 Time Mode
When the modulator operates in time mode, the modulation mark and
space periods consist of zero or an integer number of f_osc ÷ 8 clocks (=
250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 µs and
a maximum mark and space periods of about 16 ms (each). However, to
prevent carrier glitches which could affect carrier spectral purity, the
modulator control gate and carrier clock are synchronized. The carrier
signal is activated when the modulator gate opens. The modulator gate
can only close when the carrier signal is low. (The output logic level
during space periods is low). If the carrier generator is in baseband
mode (BASE bit in MCSR is high), the modulator output will be at a logic
1 for the duration of the mark period and at a logic 0 for the duration of a
space period. See Figure 9-5.
MC68HC05RC17 — Rev. 2.0
General Release Specification
Carrier Modulator Transmitter (CMT)
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