MC68HC05RC17 Datasheet, PDF (85/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Carrier Modulator Transmitter (CMT)
Modulator
9.5.4 Modulator Period Data Registers
The 12-bit MBUFF and SBUFF registers are accessed through three 8-
bit registers, MDR1, MDR2, and MDR3. MDR2 and MDR3 contain the
least significant eight bits of MBUFF and SBUFF respectively. MDR1
contains the two most significant nibbles of MBUFF and SBUFF. In
many applications, periods greater than those obtained by eight bits will
not be required. Splitting the registers up in this manner allows the user
to clear MDR1 and generate 8-bit periods with just two data writes.
MDR1 Address: $0015
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MB11 MB10 MB9
MB8 SB11 SB10 SB9
SB8
Write:
Reset:
Unaffected by Reset
MDR2 Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
Write:
Reset:
Unaffected by Reset
MDR3 Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Write:
Reset:
Unaffected by Reset
Figure 9-8. Modulator Data Registers (MDR1, MDR2, and MDR3)
MC68HC05RC17 — Rev. 2.0
General Release Specification
Carrier Modulator Transmitter (CMT)
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