MC68HC05RC17 Datasheet, PDF (57/128 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Low-Power Modes
Wait Mode
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
states. The timer may be enabled to allow a periodic exit from wait mode.
NOTE: For minimum current consumption, the phase-locked loop (PLL) should
be disabled or turned off before entering wait mode.
STOP
WAIT
STOP OSCILLATOR
AND ALL CLOCKS.
CLEAR I BIT.
OSCILLATOR ACTIVE.
IR TIMER CLOCK ACTIVE.
CORE TIMER CLOCK ACTIVE.
PROCESSOR CLOCKS
STOPPED.
LPRST
N
OR
RESET?
EXTERNAL
Y
INTERRUPT
N
(PTB KEYSCAN PULLUPS)
(IRQ)?
Y
TURN ON OSCILLATOR.
WAIT FOR TIME
DELAY TO STABILIZE.
1. FETCH RESET
VECTOR OR
2. SERVICE
INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
LPRST
N
OR
RESET?
Y
EXTERNAL
INTERRUPT
N
(PTB KEYSCAN PULLUPS)
(IRQ)?
Y
IR TIMER
INTERNAL
N
YINTERRUPT?
RESTART
PROCESSOR CLOCK.
Y
CORE TIMER
INTERNAL
N
INTERRUPT?
Y
1. FETCH RESET
VECTOR OR
2. SERVICE
INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
Figure 6-2. Stop/Wait Flowchart
MC68HC05RC17 — Rev. 2.0
General Release Specification
Low-Power Modes
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