SGTL5000XNAA3R2 Datasheet, PDF (9/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
POWER UP TIMING
Time from all supplies powered up and SYS_MCLK present to initial
communication. See Figure 4.
t_PC
1.0⁽²⁾
–
-
s
I2C BUS TIMING⁽³⁾ See Figure 5.
I²C Serial Clock Frequency
f_{I2C_CLK}
-
-
400
kHz
I²C Start condition hold time
t_I2CSH
150
-
-
ns
I²C Stop condition setup time
t_I2CSTSU
150
-
-
ns
I²C Data input setup time to rising edge of CTRL_CLK
t_I2CDSU
125
-
-
ns
I²C Data input hold time from falling edge of CTRL_CLK (receiving data)
t_I2CDH
5.0
-
-
ns
I²C Data input hold time from falling edge of CTRL_CLK (driving data)
t_I2CDH
360
-
-
ns
I²C CTRL_CLK low time
I²C CTRL_CLK high time
t_I2CCLKL
300
-
t_I2CCLKH
100
-
-
ns
-
ns
SPI BUS TIMING⁽⁴⁾ See Figure 6.
SPI Serial Clock Frequency
f_{SPI_CLK}
-
-
TBD
MHz
SPI data input setup time
SPI data input hold time
SPI CTRL_CLK low time
t_SPIDSU
10
-
t_SPIDH
10
-
t_SPICLKL
TBD
-
-
ns
-
ns
-
ns
SPI CTRL_CLK high time
t_SPICLKH
TBD
-
-
ns
SPI clock to chip select
SPI chip select to clock
t_CCS
60
-
t_CSC
20
-
-
ns
-
ns
SPI chip select low
t_CSL
20
-
-
ns
SPI chip select high
t_CSH
20
ns
SPECIFICATIONS AND TIMING FOR THE I²S PORT⁽⁵⁾ See Figure 7.
Frequency of I²S_LRCLK
Frequency of I²S_SCLK
I²S delay
I²S setup time
I²S hold time
f_LRCLK
8.0
-
96
kHz
f_SCLK
-
32*f_LRCLK
-
kHz
64*f_LRCLK
t_{I2S_D}
-
-
10
ns
t_{I2S_S}
10
-
-
ns
t_{I2S_H}
10
-
-
ns
Notes
1. The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time,
communication can start.
2. 1.0s represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK.
3. This section provides timing for the SGTL5000 while in I²C mode (CTRL_MODE = 0).
4. This section provides timing for the SGTL5000 while in SPI mode (CTRL_MODE = 1)
5. The following are the specifications and timing for I²S port. The timing applies to all formats.
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
9