SGTL5000XNAA3R2 Datasheet, PDF (13/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER
The SGTL5000 has a flexible power architecture to allow
the system designer to minimize power consumption and
maximize performance at the lowest cost.
External Power Supplies
The SGTL5000 requires 2 external power supplies: VDDA
and VDDIO. An optional third external power supply VDDD
may be provided externally to achieve lower power. This
external VDDD power supply is required for new designs. A
description for the different power supplies is as follows:
• VDDA: This external power supply is used for the internal
analog circuitry including ADC, DAC, LINE inputs, MIC
inputs, headphone outputs and reference voltages. VDDA
supply ranges are shown in Maximum Ratings. A
decoupling cap should be used on VDDA, as shown in the
typical application diagrams in Typical Applications.
• VDDIO: This external power supply controls the digital I/O
levels as well as the output level of LINE outputs. VDDIO
supply ranges are shown in Maximum Ratings. A
decoupling cap should be used on VDDIO as shown in the
typical application diagrams in Typical Applications.
Note that if VDDA and VDDIO are derived from the same
voltage, a single decoupling capacitor can be used to
minimize cost. This capacitor should be placed closest to
VDDA.
• VDDD: This is a digital power supply that is used for
internal digital circuitry. An external VDDD power supply is
required for new designs. For lowest power, this supply
can be driven at the lowest specified voltage given in
Maximum Ratings. If an external supply is used for VDDD,
a decoupling capacitor is recommended, as shown in the
typical applications diagram. VDDD supply ranges are
shown in Maximum Ratings for when externally driven. If
the system drives VDDD externally, an efficient switching
supply should be used or no system power savings is
realized.
Internal Power Supplies
The SGTL5000 has two exposed internal power supplies,
VAG and charge pump.
• VAG is the internal voltage reference for the ADC and
DAC. After startup the voltage of VAG should be set to
VDDA/2 by writing CHIP_REF_CTRL->VAG_VAL. Refer
to programming Chip Powerup and Supply Configurations.
The VAG pin should have an external filter capacitor as
shown in the typical application diagram.
• Chargepump: This power supply is used for internal
analog switches. If VDDA or VDDIO is greater than 2.7 V,
this supply is automatically driven from the highest of
VDDIO and VDDA. If both VDDIO and VDDA are less than
3.1 V, then the user should turn on the charge pump
function to create the charge pump rail from VDDIO by
writing CHIP_ANA_POWER->
VDDC_CHRGPMP_POWERUP register. Refer to
programming Chip Powerup and Supply Configurations.
• LINE_OUT_VAG is the line output voltage reference. It
should be set to VDDIO/2 by writing
CHIP_LINE_OUT_CTRL->LO_VAGCNTRL.
Power Schemes
The SGTL5000 supports a flexible architecture and allows
the system designer to minimize power or maximize BOM
savings.
• For maximum cost savings, all supplies can be run at the
same voltage.
• Alternatively for minimum power, the analog and digital
supplies can be run at minimum voltage while driving the
digital I/O voltage at the voltage needed by the system.
• To save power, independent supplies are provided for line
outputs and headphone outputs. This allows for 1VRMS
line outputs while using minimal headphone power.
• For best power, VDDA should be run at the lowest
possible voltage required for the maximum headphone
output level. For highest performance, VDDA should be
run at 3.3 V. For most applications a lower voltage can be
used for the best performance/power combination.
RESET
The SGTL5000 has an internal reset that is deasserted 8
SYS_MCLKs after all power rails have been brought up. After
this time communication can start. See Dynamic Electrical
Characteristics.
CLOCKING
Clocking for the SGTL5000 is provided by a system
master clock input (SYS_MCLK). SYS_MCLK should be
synchronous to the sampling rate (Fs) of the I²S port.
Alternatively any clock between 8.0 and 27 Mhz can be
provided on SYS_MCLK and the SGTL5000 can use an
internal PLL to derive all internal and I²S clocks. This allows
the system to use an available clock such as 12 MHz
(common USB clock) for SYS_MCLK to reduce overall
system costs.
Synchronous SYS_MCLK input
The SGTL5000 supports various combinations of
SYS_MCLK frequency and sampling frequency as shown in
Table 8. Using a synchronous SYS_MCLK allows for lower
power as the internal PLL is not used.
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
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