SGTL5000XNAA3R2 Datasheet, PDF (4/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

PIN CONNECTIONS
Table 1. SGTL5000 Pin Definitions (continued)
20 Pin QFN 32 Pin QFN Pin Name
Pin
Function
Formal Name
Definition
10
15
MIC
Analog
Microphone input
11
16
MIC_BIAS
Analog
Mic bias
—
18
CPFILT
Analog
Charge Pump Filter ^{The CPFILT cap value is 0.1 F. If both VDDIO and}
VDDA are  3.0 V, the CPFILT pin must be connected
to a 0.1 F cap to GND. If either is > 3.0 V, the CPFILT
cap MUST NOT be placed.
12
20
VDDIO
Power
Digital I/O voltage
13
21
SYS_MCLK
Digital
System master clock
14
23
I2S_LRCLK
Digital
I²S frame clock
15
24
I2S_SCLK
Digital
I²S bit clock
16
25
I2S_DOUT
Digital
I²S data output
17
26
I2S_DIN
Digital
I²S data input
18
27
CTRL_DATA
Digital _I²_{C Mode: Serial Data}
(SDA); SPI Mode: Serial
Data Input (MOSI)
19
29
CTRL_CLK
Digital _I²_{C Mode: Serial Clock}
(SCL); SPI Mode: Serial
Clock (SCK)
20
30
VDDD
Digital
Digital voltage
For new designs, connect VDDD to an external voltage
source and to a 0.1 F capacitor to GND.
-
31
CTRL_ADR0_CS Digital _I²_{C Mode: I}²_{C Address}
Select 0; SPI Mode: SPI
Chip Select
-
32
CTRL_MODE
Digital _{Mode select for I}²_{C or}
SPI; When pulled low the
control mode is I²C, when
pulled high the control
mode is SPI
PAD 1, 3, 4, PAD
GND
Ground
Ground
The PAD must be soldered to ground.
Star the ground pins of the chip, VAG ground, and all
analog inputs/outputs to a single point, then to the
ground plane.
SGTL5000
4
Analog Integrated Circuit Device Data
Freescale Semiconductor