SGTL5000XNAA3R2 Datasheet, PDF (23/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Input from
Dual Input Mixer
DAP_AVC_THRESHOLD
Threshold
Level
Compare
If < Threshold
Decay (0.05dB/s to ~200dB/s)
DAP_AVC_DECAY
DAP_AVC_THRESHOLD -> MAX_GAIN
Volume
Control
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If > Threshold
Attack (0.8dB/s to ~3200dB/s)
DAP_AVC_ATTACK
Figure 16. DAP AVC Block Diagram
When the measured audio level is below threshold, the
AVC can apply a maximum gain of up to 12 dB. The
maximum gain can be selected, either 0, 6, or 12 dB. When
the maximum gain is set to 0 dB the AVC acts as a limiter. In
this case the AVC only takes effect when the signal level is
above the threshold.
The rate at which the incoming signal is attenuated down
to the threshold is called the attack rate. Too high of an attack
causes an unnatural sound as the input signal may be
distorted. Too low of an attack may cause saturation of the
output as the incoming signal is not compressed quickly
enough. The attack rate is programmable with allowed range
of 0.05 dB/s to 200 dB/s.
When the signal is below the threshold, AVC adjusts the
volume up until either the threshold or the maximum gain is
reached. The rate at which this volume is changed is called
the decay rate. The decay rate is programmable with allowed
range of 0.8 dB/s to 3200 dB/s. It is desirable to use very slow
decay rate to avoid any distortion in the signal and prevent
the AVC from entering a continuous attack-decay loop.
Refer to Automatic Volume Control (AVC) and Automatic
Volume Control (AVC) On/Off for a programming example
that shows how to configure AVC and how to enable/disable
AVC respectively.
CONTROL
The SGTL5000 supports both I²C and SPI control modes
(note that SPI is not supported in the 20 QFN part). The
CTRL_MODE pin chooses which mode is used. When
CTRL_MODE is tied to ground, the control mode is I²C.
When CTRL_MODE is tied to VDDIO, the control mode is
SPI.
Regardless of the mode, the control interface is used for all
communication with the SGTL5000 including startup
configuration, routing, volume, etc.
I²C
The I²C port is implemented according to the I²C
specification v2.0. The I²C interface is used to read and write
all registers.
For the 32 QFN version of the SGTL5000, the I²C device
address is 0n01010(R/W) where n is determined by
CTRL_ADR0_CS and R/W is the read/write bit from the I²C
protocol.
For the 20 QFN version of the SGTL5000 the I²C address
is always 0001010(R/W).
The SGTL5000 is always the slave on all transactions,
which means that an external master always drives
CTRL_CLK.
In general, an I²C transaction looks like the following.
All locations are accessed with a 16 bit address. Each
location is 16 bits wide.
Example I²C write
• Start condition
• Device address with the R/W bit cleared to indicate write
• Send two bytes for the 16 bit register address (most
significant byte first)
• Send two bytes for the 16 bits of data to be written to the
register (most significant byte first)
• Stop condition
Example I²C read
• Start condition
• Device address with the R/W bit cleared to indicate write
• Send two bytes for the 16 bit register address (most
significant byte first)
• Stop Condition followed by start condition (or a single
restart condition)
• Device address with the R/W bit set to indicate read
• Read two bytes from the addressed register (most
significant byte first)
• Stop condition
Figure 17 shows the functional I²C timing diagram.
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
23