SGTL5000XNAA3R2 Datasheet, PDF (44/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
The Table 34, CHIP_PLL_CTRL 0x0032 register may only
be changed after reset, and before PLL_POWERUP is set.
Table 34. CHIP_PLL_CTRL 0x0032
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT_DIVISOR
FRAC_DIVISOR
BITS
FIELD
RW RESET
DEFINITION
15:11
INT_DIVISOR
RW
0xA
This is the integer portion of the PLL divisor. To determine the value of this field, use
the following calculation:
INT_DIVISOR = FLOOR(PLL_OUTPUT_FREQ/INPUT_FREQ)
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz
INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL-
>INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2) If
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
10:0
FRAC_DIVISOR
RW
0x0
This is the fractional portion of the PLL divisor. To determine the value of this field, use
the following calculation:
FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR)*2048
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz
INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL-
>INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2) If
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
Table 35, CHIP_CLK_TOP_CTRL 0x0034 has the
miscellaneous controls for the clock block.
Table 35. CHIP_CLK_TOP_CTRL 0x0034
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
RSVD
RSVD
BITS
FIELD
RW RESET
DEFINITION
15:12
RESERVED
RO
0x0
Reserved
11
ENABLE_INT_OSC RW
0x0
Setting this bit enables an internal oscillator to be used for the zero cross detectors,
the short detect recovery, and the charge pump. This allows the I²S clock to be shut
off while still operating an analog signal path. This bit can be kept on when the I²S
clock is enabled, but the I²S clock is more accurate so it is preferred to clear this bit
when I²S is present.
10:4
RSVD
RW
0x0
Reserved
SGTL5000
44
Analog Integrated Circuit Device Data
Freescale Semiconductor