SGTL5000XNAA3R2 Datasheet, PDF (14/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Table 8. Synchronous MCLK Rates and Sampling Frequencies
CLOCK
SUPPORTED RATES
System Master Clock (SYS_MCLK)
Sampling Frequency (Fs)
256, 384, 512
8, 11.025, 16, 22.05, 32, 44.1, 48, 96 ⁽⁶⁾
Notes
6. For a sampling frequency of 96 kHz, only 256 Fs SYS_MCLK is supported
UNITS
Fs
kHz
Using the PLL - Asynchronous SYS_MCLK input
An integrated PLL is provided in the SGTL5000 that allows
any clock from 8.0 to 27 MHz to be connected to SYS_MCLK.
This can help save system costs, as a clock available
elsewhere in the system can be used to derive all audio
clocks using the internal PLL. In this case, the clock input to
SYS_MCLK can be asynchronous with the sampling
frequency needed in the system. For example, a 12 MHz
clock from the system processor could be used as the clock
input to the SGTL5000.
Three register fields need to be configured to properly use
the PLL. They are CHIP_PLL_CTRL->INT_DIVISOR,
CHIP_PLL_CTRL->FRAC_DIVISOR and
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2. Figure 9
shows a flowchart that shows how to determine the values to
program in the register fields.
Yes SYS_MCLK>17MHz? No
CHIP_CLK_TOP _CTRL->INPUT_FREQ_DIV2 = 1
PLL_INPUT_FREQ = SYS_MCLK/2
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0
PLL_INPUT_FREQ = SYS_MCLK
Sampling
Yes
Frequency =
No
44.1kHz?
PLL_OUTPUT_FREQ=180 .6336 MHz
PLL_OUTPUT_FREQ=196 .608 MHz
CHIP_PLL_CTRL->INT_DIVISOR = FLOOR (PLL_OUTPUT_FREQ/INPUT_FREQ
CHIP_PLL_CTRL->FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR) * 2048
Figure 9. PLL Programming Flowchart
For example, when a 12 MHz digital signal is placed on
MCLK, for a 48 kHz frame clock
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0 //
SYS_MCLK < 17 MHz
CHIP_PLL_CTRL->INT_DIVISOR = FLOOR
(196.608 MHz/12 MHz) = 16 (decimal)
CHIP_PLL_CTRL->FRAC_DIVISOR = ((196.608 MHz/
12 MHz) - 16) * 2048 = 786 (decimal)
Refer to PLL programming PLL Configuration.
AUDIO SWITCH (SOURCE SELECT SWITCH)
The audio switch is the central routing block that controls
the signal flow from input to output. Any single input can be
routed to any single or multiple outputs.
Any signal can be routed to the Digital Audio Processor
(DAP). The output of the DAP (an input to the audio switch)
can in turn be routed to any physical output. The output of the
DAP can not be routed into itself. Refer to Digital Audio
Processing, for DAP information and configuration.
It should be noted that the analog bypass from Line input
to headphone output does not go through the audio switch.
SGTL5000
14
Analog Integrated Circuit Device Data
Freescale Semiconductor