SGTL5000XNAA3R2 Datasheet, PDF (59/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Typical connections are shown in the following application
diagrams. For new designs, and for either the 20 QFN or 32
QFN part, an external VDDD power supply connection is
required along with a 0.1 F cap connection from VDDD to
ground.
CPFILT Note: The CPFILT cap value is 0.1 F. If both
VDDIO and VDDA are  3.0 V, the CPFILT pin must be
connected to a 0.1 F cap to GND. If either is > 3.0 V, the
CPFILT cap MUST NOT be placed.
HP_VGND Note: Do not connect HP_VGND to system
ground, even when unused. This is a virtual ground (DC
voltage) that should never connect to an actual “0 Volt
ground”. Use the widest, shortest trace possible for the
HP_VGND.
32QFN Typical Application Schematic
VDDD (1.1V - 2.0V, 11mA Min)
Note: External VDDD
required for new designs.
C1
0.1uF
U1
CTRL_CLK
CTRL_DATA
I2S_DIN
I2S_DOUT
I2S_SCLK
I2S_LRCLK
Note: Capless headphone design shown here.
For cap-coupled design, see 20QFN Typical
Application Schematic.
1
J1
2
2
3
3
4
4
5
5
1
6
Audio Jack
7
8
VDDA
GND
HP_R
GND
HP_VGND
VDDA
HP_L
AGND
NC
C3
0.1uF
Notes:
1. This 32QFN schematic shows VDDD (pin 30) being derived
externally. An external VDDD is required for new designs. For
lowest power operation, VDDD can be driven from an
external 1.2V switching supply with a 0.1uF capacitor to ground.
2. If both VDDIO and VDDA are equal to or below 3V, the CPFILT pin (pin
17) must be connected to a 0.1uF capacitor to ground. If either is above
3V, this capacitor must not be placed.
SGTL5000_32QFN
C5 0.1uF
C6 1uF
LINE_OUT_R
LINE_OUT_L
C8 1uF
3. The above shows I2C implementation as CTRL_MODE (pin 32) is tied
to ground. In addition, address 0 of the I2C address is 0 as
CTRL_ADR0_CS (pin 31) is tied to ground.
4. AGND (pin 7) should be "star" connected to the jack grounds for
LINEIN and LINEOUT, and to the VAG capacitor ground. This node
should via to the ground plane (or connected to ground) at a single point.
24
I2S_SCLK
I2S_LRCLK
NC
23
22
21
SYS_MCLK ₂₀
VDDIO
NC
CPFILT
19
18
17
NC
GND ^PAD
SYS_MCLK
VDDIO
C2
0.1uF
Solder Pad to GND
C4
0.1uF
X1
1
2
MIC
C7
R1 2.2k
1uF
Note: R1 only needed if
internal BIAS_RESISTOR
settings are not suitable.
C9 1uF
C10 1uF
LINE_IN_L
LINE_IN_R
Figure 19. 32 QFN Typical Application Schematic
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
59