SGTL5000XNAA3R2 Datasheet, PDF (24/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
I2C Address
Start Condition
R/W ACK A15
A8 ACK A7
A0 ACK D15
D8 ACK D7
D0 ACK
Stop Condition
Figure 17. Functional I²C Diagram
The protocol has an auto increment feature. Instead of
sending the stop condition after two bytes of data, the master
may continue to send data byte pairs for writing, or it may
send extra clocks for reading data byte pairs. In either case,
the access address is incremented after every two bytes of
data. A start or stop condition from the I²C master interrupts
the current command. For reads, unless a new address is
written, a new start condition with R/W=0 reads from the
current address and continues to auto increment.
The following diagrams describe the different access
formats. The gray fields are from the I²C master, and the
white fields are the SGTL5000 responses. Data [n]
corresponds to the data read from the address sent,
data[n+1] is the data from the next register, and so on.
S = Start Condition
Sr = Restart Condition
A = Ack
N = Nack
P = Stop Condition
Table 11. Write Single Location
S
Device
Address
W
A
ADDR
A
ADDR
A
DATA
A
DATA
AP
(0)
byte 1
byte 0
byte 1
byte 0
Table 12. Write Auto increment
S
Device
WA
start
A
start
A DATA A DATA A DATA A DATA A P
Address
(0)
ADDR
ADDR
[n]
[n]
[n+1]
[n+1]
byte 1
byte 0
byte 1
byte 0
byte 1
byte 0
Table 13. Read Single Location
S
Device
Address
W A ADDR A ADDR A Sr
(0)
byte 1
byte 0
Device
Address
R A DATA A DATA N P
(1)
byte 1
byte 0
Table 14. Read Auto increment
S Device W A start A start A Sr
Address (0)
ADDR
ADDR
byte 1
byte 0
Device
Address
R A DATA A DATA A DATA A DATA N P
(1)
[n]
[n]
[n+1]
[n+1]
byte 1
byte 0
byte 1
byte 0
Table 15. Read Continuing Auto increment
S
Device
Address
R
A
DATA
A
DATA
A
DATA
A
DATA
NP
[n+2]
[n+2]
[n+3]
[n+3]
byte 1
byte 0
byte 1
byte 0
SPI
Serial Peripheral Interface (SPI) is a communications
protocol supported by the SGTL5000 (not supported in the 20
QFN package). The SGTL5000 is always a slave. The
CTRL_ADR0_CS is used as the slave select (SS) when the
master wants to select the SGTL5000 for communication.
CTRL_CLK is connected to master’s SCLK and CTRL_DATA
is connected to master’s MOSI line. The part only supports
SPI write operations and does not support read operations.
Figure 18 shows the functional timing diagram of the SPI
communication protocol as supported by the SGTL5000 chip.
Note that on the rising edge of the SS, the chip latches to the
previous 32 bits of data. It interprets the latest 16-bits as
register value and the 16-bits preceding it as register
address.
SGTL5000
24
Analog Integrated Circuit Device Data
Freescale Semiconductor