SGTL5000XNAA3R2 Datasheet, PDF (42/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
The Table 33, CHIP_ANA_POWER 0x0030 register
contains all of the power down controls for the analog blocks.
The only other power-down controls are BIAS_RESISTOR in
Table 33. CHIP_ANA_POWER 0x0030
15
14
13
12
11
10
9
8
the MIC_CTRL register and the EN_ZCD control bits in
ANA_CTRL.
7
6
5
4
3
2
1
0
BITS
15
14
FIELD
RW
RSVD
RW
DAC_MONO
RW
13 LINREG_SIMPLE_PO RW
WERUP
12 STARTUP_POWERUP RW
11 VDDC_CHRGPMP_PO RW
WERUP
10
PLL_POWERUP
RW
9 LINREG_D_POWERUP RW
RESET
0x0
0x1
0x1
0x1
0x0
0x0
0x0
DEFINITION
Reserved
While DAC_POWERUP is set, this allows the DAC to be put into left only mono
operation for power savings.
0x0 = Mono (left only)
0x1 = Stereo
Power up the simple (low power) digital supply regulator. After reset, this bit can be
cleared IF VDDD is driven externally OR the primary digital linreg is enabled with
LINREG_D_POWERUP
0x0 = Power down
0x1 = Power up
Power up the circuitry needed during the power up ramp and reset. After reset this bit
can be cleared if VDDD is coming from an external source.
0x0 = Power down
0x1 = Power up
Power up the VDDC charge pump block. If neither VDDA or VDDIO is 3.0 V or larger
this bit should be cleared before analog blocks are powered up.
0x0 = Power down
0x1 = Power up
Note that for charge pump to function, either the PLL must be powered on and
programmed correctly (refer to CHIP_CLK_CTRL->MCLK_FREQ description) or the
internal oscillator (set CLK_TOP_CTRL->ENABLE_INT_OSC) must be enabled
PLL Power Up
0x0 = Power down
0x1 = Power up
When cleared, the PLL is turned off. This must be set before CHIP_CLK_CTRL ->
MCLK_FREQ is programmed to 0x3. The CHIP_PLL_CTRL register must be
configured correctly before setting this bit.
Power up the primary VDDD linear regulator.
0x0 = Power down
0x1 = Power up
SGTL5000
42
Analog Integrated Circuit Device Data
Freescale Semiconductor