SGTL5000XNAA3R2 Datasheet, PDF (34/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
Table 21. CHIP_ADCDAC_CTRL 0x000E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RSVD
RSVD
BITS
FIELD
RW
15:14
RSVD
RO
13 VOL_BUSY_DAC_RIG RO
HT
12 VOL_BUSY_DAC_LEF RO
T
11:10
9
RSVD
RO
VOL_RAMP_EN
RW
8
VOL_EXPO_RAMP RW
7:4
RSVD
RW
3
DAC_MUTE_RIGHT RW
2
DAC_MUTE_LEFT RW
1
ADC_HPF_FREEZE RW
0
ADC_HPF_BYPASS RW
RESET
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x1
0x1
0x0
0x0
DEFINITION
Reserved
Volume Busy DAC Right
0x0 = Ready
0x1 = Busy - This indicates the channel has not reached its programmed volume/mute
level
Volume Busy DAC Left
0x0 = Ready
0x1 = Busy - This indicates the channel has not reached its programmed volume/mute
level
Reserved
Volume Ramp Enable
0x0 = Disables volume ramp. New volume settings take immediate effect without a
ramp
0x1 = Enables volume ramp
This field affects DAC_VOL. The volume ramp effects both volume settings and mute.
When set to 1 a soft mute is enabled.
Exponential Volume Ramp Enable
0x0 = Linear ramp over top 4 volume octaves
0x1 = Exponential ramp over full volume range
This bit only takes effect if VOL_RAMP_EN is 1.
Reserved
DAC Right Mute
0x0 = Unmute
0x1 = Muted
If VOL_RAMP_EN = 1, this is a soft mute.
DAC Left Mute
0x0 = Unmute
0x1 = Muted
If VOL_RAMP_EN = 1, this is a soft mute.
ADC High Pass Filter Freeze
0x0 = Normal operation
0x1 = Freeze the ADC high-pass filter offset register. The offset continues to be
subtracted from the ADC data stream.
ADC High Pass Filter Bypass
0x0 = Normal operation
0x1 = Bypassed and offset not updated
SGTL5000
34
Analog Integrated Circuit Device Data
Freescale Semiconductor