SGTL5000XNAA3R2 Datasheet, PDF (18/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the left subframe should always be presented first regardless
of the CHIP_I2S_CTRL->LRPOL setting.
The I2S_LRCLK and I2S_SCLK can be programmed as
master (driven to an external target) or slave (driven from an
external source). When the clocks are in slave mode, they
must be synchronous to SYS_MCLK. For this reason the
SGTL5000 can only operate in synchronous mode (see
Clocking) while in I²S slave mode.
In master mode, the clocks are synchronous to
SYS_MCLK or the output of the PLL when the part is running
in asynchronous mode.
Figure 10 shows functional examples of different common
digital interface formats and their associated register
settings.
I2S Format (n = bit length)
CHIP_I2S0_CTRL field values:
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 0; LRPOL = 0)
I2S_LRCLK
I2S_SCLK
I2S_DIN, DOUT
Ln L(n-1)
L01 L00
Rn R(n-1)
R01 R00
Ln
Left Justified Format (n = bit length)
CHIP_I2S0_CTRL field values:
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 1; LRPOL = 0)
I2S_LRCLK
I2S_SCLK
I2S_DIN, DOUT
Ln L(n-1)
L1 L0
Rn R(n-1)
R1 R0
Ln L(n-1)
Right Justified Format (n = bit length)
CHIP_I2S0_CTRL field values:
SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 1; LRALIGN = 1; LRPOL = 0)
I2S_LRCLK
I2S_SCLK
I2S_DIN, DOUT
Ln L(n-1)
L0
Rn R(n-1)
R0
Figure 10. I²S Port Supported Formats
SGTL5000
18
Analog Integrated Circuit Device Data
Freescale Semiconductor