SGTL5000XNAA3R2 Datasheet, PDF (15/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
To configure a route, the CHIP_SSS_CTRL register is
used. Each output from the source select switch has its own
register field that is used to select what input is routed to that
output.
For example, to route the I²S digital input through the DAP
and then out to the DAC (headphone) outputs write
SSS_CTRL->DAP_SELECT to 0x1 (selects I2S_IN) and
SSS_CTRL->DAC_SELECT to 0x3 (selects DAP output).
ANALOG INPUT BLOCK
The analog input block contains a stereo line input and a
microphone input with mic bias. Either input can be routed to
the ADC. The line input can also be configured to bypass the
CODEC and be routed directly to the headphone output.
Line Inputs
One stereo line input is provided for connection to line
sources such as an FM radio or MP3 input.
The source should be connected to the left and right line
inputs through series coupling capacitors. The suggested
value is shown in the typical application diagram in Typical
Applications.
As detailed in ADC, the line input can be routed to the
ADC.
The line input can also be routed to the headphone output
by writing CHIP_ANA_CTRL->SELECT_HP. This selection
bypasses the ADC and audio switch and routes the line input
directly to the headphone output to enable a very low power
pass through.
Microphone Input
One mono microphone input is provided for uses such as
voice recording.
Mic bias is provided. The mic bias is programmed with the
CHIP_MIC_CTRL->BIAS_VOLT register field. Values from
1.25 V to 3.00 V are supported in 0.25 V steps. Mic bias
should be set less than 200 mV from VDDA, e.g. with VDDA
at 1.70 V, Mic bias should be set no greater than 1.50 V.
The microphone should be connected through a series
coupling capacitor. The suggested value is shown in the
typical connection diagram.
The microphone has programmable gain through the
CHIP_MIC_CTRL->GAIN register field. Values of 0 dB,
+20 dB, +30 dB and +40 dB are available.
ADC
The SGTL5000 contains an ADC, which takes its input
from either the line input or a microphone. The register field
CHIP_ANA_CTRL->SELECT_ADC controls this selection.
The output of the ADC feeds the audio switch.
The ADC has its own analog gain stage that provides 0 to
+22.5 dB of gain in 1.5 dB steps. A bit is available that shifts
this range down by 6.0 dB to effectively provide -6.0 dB to
+16.5 dB of gain. The ADC gain is controlled in the
CHIP_ANA_ADC_CTRL register.
The ADC has an available zero cross detect (ZCD) that
prevents any volume change until a zero-volt crossing of the
audio signal is detected. This helps in eliminating pop or other
audio anomalies. If the ADC is to be used, the chip reference
bias current should not be set to -50% when in 3.0 V mode.
ANALOG OUTPUTS
The SGTL5000 contains a single stereo DAC that can be
used to drive a headphone output and a line output. The DAC
receives its input from the audio switch. The headphone
output and the line output can be driven at the same time
from the DAC.
The headphone output can also be driven directly by the
line input bypassing the ADC and DAC for a very low power
mode of operation.
The headphone output is powered by VDDA while the line
output is powered by VDDIO. This allows the headphone
output to be run at the lowest possible voltage while the line
output can still meet line output level requirements.
DAC
The DAC output is routed to the headphone and the
dedicated line output.
The DAC output has a digital volume control from -90 dB
to 0 dB in ~0.5 dB step sizes. This volume is shared among
headphone output and line output. The register
CHIP_DAC_VOL controls the DAC volume.
Headphone
Stereo headphone outputs are provided which can be
used to drive a headphone load or a line level output. The
headphone output has its own independent analog volume
control with a volume range of -52 dB to +12 dB in 0.5 dB
step sizes. This volume control can be used in addition to the
DAC volume control. For best performance the DAC volume
control should be left at 0 dB until the headphone is brought
to its lowest setting of -52 dB. The register
CHIP_ANA_HP_CTRL is used to control the headphone
volume.
The headphone output has an independent mute that is
controlled by the register field CHIP_ANA_CTRL-
>MUTE_HP.
The line input is routed to the headphone output by writing
CHIP_ANA_CTRL->SELECT_HP. This selection bypasses
the ADC and audio switch and routes the line input directly to
the headphone output to enable a very low power pass
through. When the line input is routed to the headphone
output, only the headphone analog volume and mute affects
the headphone output.
The headphone has an available zero cross detect (ZCD)
which, as previously described, prevents any volume change
until a zero-volt crossing of the audio signal is detected. This
helps in eliminating pop or other audio anomalies.
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
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