SGTL5000XNAA3R2 Datasheet, PDF (27/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
Write CHIP_ANA_CTRL
0x0133
//------------Power up Inputs/Outputs/Digital Blocks---------
// Power up LINEOUT, HP, ADC, DAC
Write CHIP_ANA_POWER 0x6AFF
// Power up desired digital blocks
// I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5),
// ADC (bit 6) are powered on
Write CHIP_DIG_POWER 0x0073
//----------------Set LINEOUT Volume Level-------------------
// Set the LINEOUT volume level based on voltage reference
(VAG)
// values using this formula
// Value = (int)(40*log(VAG_VAL/LO_VAGCNTRL) + 15)
// Assuming VAG_VAL and LO_VAGCNTRL is set to 0.9 V and
1.65 V respectively, the // left LO vol (bits 12:8) and right LO
volume (bits 4:0) value should be set // to 5
Write CHIP_LINE_OUT_VOL 0x0505
System MCLK and Sample Clock
// Configure SYS_FS clock to 48 kHz
// Configure MCLK_FREQ to 256*Fs
Modify CHIP_CLK_CTRL->SYS_FS 0x0002 // bits 3:2
Modify CHIP_CLK_CTRL->MCLK_FREQ 0x0000 // bits 1:0
// Configure the I²S clocks in master mode
// NOTE: I²S LRCLK is same as the system sample clock
Modify CHIP_I2S_CTRL->MS 0x0001 // bit 7
PLL Configuration
These programming steps are needed only when the PLL
is used. Refer to Using the PLL - Asynchronous SYS_MCLK
input for details on when to use the PLL.
To avoid any pops/clicks, the outputs should be muted
during these chip configuration steps. Refer to Volume
Control for volume and mute control.
// Power up the PLL
Modify CHIP_ANA_POWER->PLL_POWERUP 0x0001 // bit 10
Modify CHIP_ANA_POWER->VCOAMP_POWERUP 0x0001 //
bit 8
// NOTE: This step is required only when the external SYS_MCLK
// is above 17 MHz. In this case the external SYS_MCLK clock
// must be divided by 2
Modify CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 0x0001 //
bit 3
Sys_MCLK_Input_Freq = Sys_MCLK_Input_Freq/2;
// PLL output frequency is different based on the sample clock
// rate used.
if (Sys_Fs_Rate == 44.1 kHz)
PLL_Output_Freq = 180.6336 MHz
else
PLL_Output_Freq = 196.608 MHz
// Set the PLL dividers
Int_Divisor = floor(PLL_Output_Freq/Sys_MCLK_Input_Freq)
Frac_Divisor = ((PLL_Output_Freq/Sys_MCLK_Input_Freq) -
Int_Divisor)*2048
Modify CHIP_PLL_CTRL->INT_DIVISOR Int_Divisor // bits 15:11
Modify CHIP_PLL_CTRL->FRAC_DIVISOR Frac_Divisor // bits
10:0
Input/Output Routing
To avoid any pops/clicks, the outputs should be muted
during these chip configuration steps. Refer to Volume
Control for volume and mute control.
A few example routes are shown below:
// Example 1: I2S_IN -> DAP -> DAC -> LINEOUT, HP_OUT
// Route I2S_IN to DAP
Modify CHIP_SSS_CTRL->DAP_SELECT 0x0001 // bits 7:6
// Route DAP to DAC
Modify CHIP_SSS_CTRL->DAC_SELECT 0x0003 // bits 5:4
// Select DAC as the input to HP_OUT
Modify CHIP_ANA_CTRL->SELECT_HP 0x0000 // bit 6
// Example 2: MIC_IN -> ADC -> I2S_OUT
// Set ADC input to MIC_IN
Modify CHIP_ANA_CTRL->SELECT_ADC 0x0000 // bit 2
// Route ADC to I2S_OUT
Modify CHIP_SSS_CTRL->I2S_SELECT 0x0000 // bits 1:0
// Example 3: LINEIN -> HP_OUT
// Select LINEIN as the input to HP_OUT
Modify CHIP_ANA_CTRL->SELECT_HP 0x0001 // bit 6
DIGITAL AUDIO PROCESSOR CONFIGURATION
To avoid any pops/clicks, the outputs should be muted
during these chip configuration steps. Refer to Volume
Control for volume and mute control.
// Enable DAP block
// NOTE: DAP will be in a pass-through mode if none of DAP
// sub-blocks are enabled.
Modify DAP_CONTROL->DAP_EN 0x0001 // bit 0
Dual Input Mixer
These programming steps are needed only if dual input
mixer feature is used.
// Enable Dual Input Mixer
Modify DAP_CONTROL->MIX_EN 0x0001 // bit 4
// NOTE: This example assumes mix level of main and mix
// channels as 100% and 50% respectively
// Configure main channel volume to 100% (No change from input
// level)
Write DAP_MAIN_CHAN 0x4000
// Configure mix channel volume to 50% (attenuate the mix
// input level by half)
Write DAP_MIX_CHAN 0x4000
Freescale Surround
The Freescale Surround on/off function is typically
controlled by the end-user. End-user driven programming
steps are shown in End-user Driven Chip Configuration.
The default WIDTH_CONTROL of 4 should be appropriate
for most applications. This optional programming step shows
how to configure a different width value.
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
27