SGTL5000XNAA3R2 Datasheet, PDF (45/68 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
BITS
FIELD
RW RESET
DEFINITION
3
INPUT_FREQ_DIV2 RW
0x0
SYS_MCLK divider before PLL input
0x0 = pass through
0x1 = SYS_MCLK is divided by 2 before entering PLL
This must be set when the input clock is above 17 Mhz. This has no effect when the
PLL is powered down.
2:0
RSVD
RW
0x0
Reserved
Status bits for analog blocks are found in Table 36,
CHIP_ANA_STATUS 0x0036
Table 36. CHIP_ANA_STATUS 0x0036
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RSVD
RSVD
BITS
FIELD
RW RESET
DEFINITION
15:10
RSVD
RO
0x0
Reserved
9
LRSHORT_STS
RO
0x0
This bit is high whenever a short is detected on the left or right channel headphone
drivers.
0x0 = Normal
0x1 = Short detected
8
CSHORT_STS
RO
0x0
This bit is high whenever a short is detected on the capless headphone common/
center channel driver.
0x0 = Normal
0x1 = Short detected
7:5
RSVD
RO
0x0
Reserved
4
PLL_IS_LOCKED RO
0x0
This bit goes high after the PLL is locked.
0x0 = PLL is not locked
0x1 = PLL is locked
3:0
RSVD
RO
0x0
Reserved
Table 37, CHIP_ANA_TEST1 0x0038 and Table 38,
CHIP_ANA_TEST2 0x003A register controls are intended
only for debug.
Table 37. CHIP_ANA_TEST1 0x0038
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HP_IALL_ADJ HP_I1_ADJ
HP_ANTIPOP
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
45