MC68HC55 Datasheet, PDF (9/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

3.1 DSI Channel 0 Data Registers
MC68HC55 Technical Data
DSI Channel 0 Data Registers
Address: $000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIt 15
14
13
Write:
12
11
10
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Figure 3-1. DSI Channel 0 Data Register Upper Byte (DSI0H)
Address: $001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIt 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 3-2. DSI Channel 0 Data Register Lower Byte (DSI0L)
Reads access the receive data FIFO for channel 0. A receive FIFO not
empty (RFNE0) status bit in the DSISTAT register indicates when it is
appropriate to read the DSI0H and DSI0L register pair. Reading DSI0L,
while the receive FIFO is not empty, causes a receive FIFO pop. In the
case of reading the 16-bit DSI0H:DSI0L register pair, read DSI0H first so
the receiver FIFO pop does not occur prematurely. Writes access the
transmit data FIFO for channel 0. A transmit FIFO not full (TFNF0) status
bit in the DSISTAT register indicates when it is appropriate (TFNF0 = 1)
to write to the DSI0H and DSI0L register pair. Writing DSI0L causes a
transmit FIFO push. In the case of writing the 16-bit DSI0H:DSI0L
register pair, write DSI0H first so the FIFO push does not occur
prematurely. Both receive and transmit are equipped with 4-stage
FIFOs.
MC68HC55
Registers and Bit Descriptions
Technical Data
9