MC68HC55 Datasheet, PDF (6/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Pin # Pin Name
1
SCLK
2
CLK
3
DI
4
DO
5
CS
6
RESET
7
INT
8
GND
9
DSI1R
10
DSI1S
11
DSI1F
12
N/C
13
DSI0R
14
DSI0S
15
DSI0F
16
V_DD
Table 2-1. Pin Information
Description
System clock
SPI clock
SPI data in to DSI/D
SPI data out from DSI/D
SPI chip select
DSI/D reset
Interrupt output
Supply common
DSI channel 1 return
DSI channel 1 signal
DSI channel 1 frame
No connection
DSI channel 0 return
DSI channel 0 signal
DSI channel 0 frame
Positive supply
Direction
Relative to DSI/D
Input
Input
Input
Three-state output
Active low input
Active low input
Active low output
(open-drain)
—
CMOS input
CMOS output
CMOS output
—
CMOS input
CMOS output
CMOS output
—
Source/
Destination
From MCU
SCK out from MCU
MOSI from MCU
MISO to MCU
Port output from MCU
RESET of MCU system
To IRQ input of MCU
Supply common
From DSI_R of DSI/P
To DSI_S of DSI/P
To DSI_F of DSI/P
—
From DSI_R of DSI/P
To DSI_S of DSI/P
To DSI_F of DSI/P
—
2.2 Pin Function Descriptions
SCLK — This clock input controls bit and frame timing for messages
between the DSI/D and the DSI/P. The length of a bit time may be
configured to be 3, 6, 12, or 24 periods of SCLK by the setting of the
CDIV0[B:A] and CDIV1[B:A] bit fields (the setting for each DSI/D
channel is independently controlled). SCLK is relatively slow (nom.
15 kHz to 450 kHz) compared to the SPI clock (nom. 4 MHz).
CLK — This is the SPI clock signal from the MCU. The DSI/D is a slave
SPI device.
DI — SPI data in to DSI/D (MOSI pin of MCU).
DO — SPI data out from DSI/D (MISO pin of MCU).
Technical Data
6
MC68HC55
MC68HC55CD Pin Assignments and Descriptions