MC68HC55 Datasheet, PDF (8/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
line. A logic 0 starts with a falling edge on DSI0S and is low for two-thirds
of the bit time and then high for one-third of the bit time. A logic 1 starts
with a falling edge on DSI0S and is low for one-third of the bit time and
then high for two-thirds of the bit time.
DSI0F — DSI channel 0 frame. This output idles high and is driven low
during each transfer frame.
V_DD — This is the positive voltage supply input (nom. 5 V).
Section 3. Registers and Bit Descriptions
The MC68HC55 includes eight 8-bit registers. A master MCU reads from
or writes to these registers through an SPI. For more information about
the SPI and command protocol, refer to 4.4 SPI Communications
Register
Address
000
001
010
011
100
101
110
111
Table 3-1. Register Summary
Register
Name
DSI0H
DSI0L
DSI1H
DSI1L
DSISTAT
DSI0CTRL
DSI1CTRL
DSIENABLE
Description
DSI channel 0 data register (upper byte)
DSI channel 0 data register (lower byte)
DSI channel 1 data register (upper byte)
DSI channel 1 data register (lower byte)
DSI status register
DSI channel 0 control register
DSI channel 1 control register
DSI channel enable bits
Technical Data
8
MC68HC55
Registers and Bit Descriptions