MC68HC55 Datasheet, PDF (35/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Timing Characteristics for DSI/D to DSI/P Interface
Parameter⁽¹⁾
Symbol Min
Typ
Communication rate (MC68HC55 to DSI/P)
—
5
—
Signal bit time (t_SCLKCYC * 3, 6, 12, or 24)
t_Bit
6.67
—
Master clock cycle time
t_SCLKCYC 2.22
t_Bit/3
Master clock duty cycle
—
40
50
Frame start to signal delay time
t_DLY1
t_Bit–0.2
t_Bit
Signal end to frame end delay time
t_DLY2
–0.2
0
Signal low time for logic 0
(33.3% duty cycle guaranteed by design)
t0_LO ²_{/3tBit–0.2} ²_/3tBit
Signal low time for logic 1
(66.7% duty cycle guaranteed by design)
t1_LO ¹_{/3tBit–0.2} ¹_/3tBit
Receive data setup — DSI1R, DSI0R
t_RSU
20
—
Receive data hold — DSI1R, DSI0R
t_RH
20
—
Rise time (20% V_DD to 70% V_DD)
DSI1F, DSI1S, DSI0F, DSI0S
t_Rise
—
—
Fall time (70% V_DD to 20% V_DD)
DSI1F, DSI1S, DSI0F, DSI0S
t_Fall
—
—
1. 4.5 volts ≤ V_DD ≤ 5.5 volts; –40°C ≤ T_AMB ≤ 85°C; C ≤ 100 pF load on all DSI/D to DSI/P pins
Max
150
200
66.7
60
t_Bit+0.2
0.2
Units
kbits/s
µs
µs
%
µs
µs
2_/3tBit+0.2
µs
1_/3tBit+0.2
µs
—
ns
—
ns
100
ns
100
ns
DSIxF
DSIxS
DSIxR
t_DLY1
t_DLY2
LOGIC 0 BIT TIME
LOGIC 1 BIT TIME
t_Bit
t_Bit
t_Fall
t_Rise
LAST CRC BIT TIME
t0_LO
t1_LO
t_RSU
t_RH
Figure 5-1. DSI/D to DSI/P Interface Timing
MC68HC55
Timing and Electrical Specifications
Technical Data
35