MC68HC55 Datasheet, PDF (18/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Section 4. Functional Description
The MC68HC55 is controlled by a master MCU through an SPI, and
handles the digital portions of a distributed system interface (DSI)
system. This device includes two separate DSI channels, each capable
of interfacing to up to 15 DSI bus slave devices (nodes). The DSI
physical layer uses a 2-wire bus with analog wave-shaped voltage and
current signals so an analog SmartMOS device called a DSI/P is needed
to interface the CMOS logic levels of the DSI/D to the analog physical
layer of the DSI bus. Refer to Figure 4-1 for the following discussions.
Major subsystems within the MC68HC55 include:
• Serial peripheral interface (SPI) to the master MCU
• A register pointer block
• Two channels of DSI data registers buffers:
– Transmit data register (high and low bytes)
– Receive data register (high and low bytes)
• CRC block for each channel
• Control and status registers
• Serial clock (SCLK) input block
• 4-level FIFOs on each transmit and receive buffer.
Technical Data
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MC68HC55
Functional Description