MC68HC55 Datasheet, PDF (13/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

3.4 DSI Channel Control Registers
MC68HC55 Technical Data
DSI Channel Control Registers
Address: $101
Bit 7
6
5
4
3
2
1
Bit 0
Read:
CDIV0B CDIV0A DLY0B DLY0A RIE0 TIE0
0
MS0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 3-6. DSI Channel 0 Control Register (DSI0CTRL)
This register should be written before data is sent over the DSI bus. Any
write to this register causes any DSI transfer in progress on this DSI
channel to be aborted (see 4.2 Abort Function). The bits in this register
are updated as they are received over the SPI, but no new values take
effect until the next DSI clock cycle after the conclusion of the SPI write
to this register.
CDIV0[B:A] — Clock Divider for Channel 0 Bits
The CDIV0[B:A] bits specify an additional divider between the SCLK
input and the bit timing circuitry.
When CDIV0[B:A] are set for 0:0, each bit time on the DSI/D to DSI/P
interface is three SCLK periods long.
Table 3-2. CDIV0 Divider Information
CDIV0[B:A]
0:0
0:1
1:0
1:1
Divisor
÷1
÷2
÷4
÷8
SCLK Periods
per Bit Time
3
6
12
24
DLY0[B:A] — Inter-Frame Delay for Channel 0 Bits
These bits specify the minimum delay between transfer frames on the
DSI/D to DSI/P interface. When DLY0[B:A] are set for 0:0, there will
be a minimum of four bit times of idle line from the end of a transfer
MC68HC55
Registers and Bit Descriptions
Technical Data
13