MC68HC55 Datasheet, PDF (30/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
satisfied, the DSIxF pin will go low, indicating the start of a new transfer
frame.
Data is shifted out of DSIxS (MSB first) and shifted in to DSIxR at the
same time. As a message is received it is stored bit-by-bit into the next
available receive FIFO location (if the FIFO is already full, an internal
overflow flag is set and the serial receive data is lost). For each data
value in the receive FIFO, there is a 1-bit status flag to indicate if there
was a CRC error while receiving the data. At the end of a DSI transfer
(and after the CRC error status is stable), the RFNEx flag is set (if it
wasn’t already) to indicate there is data in the receive FIFO to be read.
4.6 CRC Generation/Checking
Whenever a message is sent from the DSI/D to the DSI/P, a 4-bit CRC
value is computed and serially sent as the next four bits after the LSB
(least significant bit) of the data. The DSI/P passes the message,
including the CRC bits, along to a remote peripheral which computes a
separate CRC value as the message data is received. If this computed
CRC does not agree with the CRC value received in the message, the
peripheral device considers the message invalid.
Messages received by the DSI/D include a 4-bit CRC value which was
computed in the peripheral device that is responding to the DSI/D. As the
DSI/D receives a message, it computes a separate 4-bit CRC value and
compares this with the CRC value in the received message. If these
values do not agree, the message is considered invalid and the ERx
status flag is set as the receive data is transferred into the receive data
buffer.
When no remote peripheral responds to a DSI/D message, the data
pattern received by the DSI/D will be all 0s with a CRC value of 0000
which is detected as a CRC error. The correct CRC value for a $00 or
$0000 message would be 1010. The same 1010 CRC value applies for
both 8- and 16-bit messages of all 0s.
CRC errors are indicated by the ER0 and ER1 status bits. ERx status
bits are cleared when new data is transferred from the shifter to the read
data buffer and the CRC value was correct.
Technical Data
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MC68HC55
Functional Description