MC68HC55 Datasheet, PDF (34/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
5.2 DC Electrical Characteristics
Parameter⁽¹⁾
Supply current
SCLK = 450 kHz
Input high voltage
SCLK, CLK, DI, CS, RESET, DSI1R, DSI0R
Input low voltage
SCLK, CLK, DI, CS, RESET, DSI1R, DSI0R
Output high voltage (@I_OH = –800 µA)
DO, INT, DSI1F, DSI0F, DSI1S, DSI0S
Output low voltage (@I_OL = 800 µA)
DO, INT, DSI1F, DSI0F, DSI1S, DSI0S
Input leakage
SCLK, CLK, DI, CS, RESET, DSI1R, DSI0R
I/O port three-state leakage
DO
1. 4.5 volts ≤ V_DD ≤ 5.5 volts; –40°C ≤ T_AMB ≤ 85°C
Symbol Min
I_DD
—
Max
Units
3
mA
V_IH
0.7*V_DD V_DD+0.3
V
V_IL
–0.3
0.3*V_DD
V
V_OH
0.8*V_DD
V_DD
V
V_OL
0.0
0.2*V_DD
V
I_In
—
±10
µA
I_OZ
—
±10
µA
5.3 Timing Characteristics for DSI/D to DSI/P Interface
This section describes the AC timing characteristics of the DSI/D to
DSI/P interface pins (DSIxF, DSIxS, DSIxR). The signal bit time is
derived by dividing the master clock input (SCLK) by 3, 6, 12, or 24 (see
Figure 3-7 description of CDIVx[B:A] control bits). The bit time (t_Bit) is
then used as the basis for other timing specifications.
Technical Data
34
MC68HC55
Timing and Electrical Specifications